A Hybrid-parallel Architecture for Applications in Bioinformatics

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Weitere TitelZusatztitel :
  • Zugl.: Kiel, Univ., Diss. 2017
Beteiligte Person(en) / Institution(en)Autor :
DatumErschienen :
  • November 2017
Seitenbereichxv, 184 S.

Since the advent of Next Generation Sequencing (NGS) technology, the amount of data from whole genome sequencing has been rising fast. In turn, the availability of these resources led to the tapping of whole new research fields in molecular and cellular biology, producing even more data. On the other hand, the available computational power is only increasing linearly.
In recent years though, special-purpose high-performance devices started to become prevalent in today’s scientific data centers, namely graphics processing units (GPUs) and, to a lesser extent, field-programmable gate arrays (FPGAs). Driven by the need for performance, developers started porting regular applications to GPU frameworks and FPGA configurations to exploit the special operations only these devices may perform in a timely manner.
However, applications using both accelerator technologies are still rare. Major challenges in joint GPU/FPGA application development include the required deep knowledge of associated programming paradigms and the efficient communication both types of devices. In this work, two algorithms from bioinformatics are implemented on a custom hybrid-parallel hardware architecture and a highly concurrent software platform. It is shown that such a solution is not only possible to develop but also its ability to outperform implementations on similarsized GPU or FPGA clusters in terms of both performance and energy consumption. Both algorithms analyze case/control data from genomewide association studies to find interactions between two or three genes with different methods. Especially in the latter case, the newly available calculation power and method enables analyses of large data sets for the first time without occupying whole data centers for weeks. The success of the hybrid-parallel architecture proposal led to the development of a highend array of FPGA/GPU accelerator pairs to provide even better runtimes and more possibilities.
Statische URLhttps://www.uni-kiel.de/journals/receive/jportal_jparticle_00000335
 
URN:NBNurn:nbn:de:gbv:8:1-zs-00000335-a3
IDDOI :
  • 10.21941/kcss/2017/04
Nummer des Berichts :
  • 2017/4